`timescale 10ns/1ns
module tb_fifo();

reg clk;
reg rst_n;
reg pop;
reg push;
reg [15:0] din;
wire [15:0] dout;

initial begin 
  $dumpfile("test.vcd");
  $dumpvars(0,tb_fifo);

  clk = 0; rst_n = 0; pop = 0; push = 0; din = 16'b0;
  #100 rst_n =1; pop = 1;
  #100 pop = 1;
  #100 pop = 1;
  #100 pop = 1;
  #100 push = 1; pop = 0; din = 16'hAAAA;
  #100 push = 1; din = 16'hBBBB;
  #100 push = 1; din = 16'hCCCC;
  #100 push = 1; din = 16'hDDDD;
  #100 push = 1; din = 16'hEEEE;
  #100 pop = 1; push = 0; din = 16'h0000;
  #100 pop = 1;
  #100 pop = 1;
  #100 pop = 1;
  #100 rst_n = 0; pop = 0;
  #100 rst_n = 1; pop = 1;
  #100 pop = 1;
  #100 $finish;
end

always #50 clk = !clk;

fifo DUT (
  .din(din[15:0]),
  .clk(clk),
  .rst_n(rst_n),
  .pop(pop),
  .push(push),
  .dout(dout[15:0])
);
endmodule
